Realization of readout integrated circuit (ROIC) for an array of 288x4, N-on-P type HgCdTe long wave infrared detectors

Infrared (IR) imaging systems are used in a variety of applications from biomedical to astronomic and strategic imaging. Modern military missile guidance and surveillance systems also incorporate infrared imaging systems. The most critical component of an infrared imaging system is the focal plane array (FPA), a key assembly of detectors and readout electronics to carry out the function of infrared to electrical signal conversion. As in all sensor networks, extraordinary care must be given to both the detector design and readout integrated circuits, to obtain a high performance and durable system. In IRFPAs, detectors set the operation wavelength, readout circuit area and operation temperature. However many of the system performance parameters such as signal to noise ratio (SNR), linearity, input referred noise level, dynamic range, are set by the readout integrated circuit (ROIC). First generation of IR imaging systems incorporated single detector, or a fewer number of detectors. Higher frame rate and resolution requirements brought up the scanning type of FPAs where a scene is scanned constantly to create a 2D electronic image by a single array of detectors. Scanning type FPAs, with higher frame rates, started to replace staring arrays, with the maturing of detector processing technology and allowing integration of thousands of functioning detectors (pixels) on a single substrate, with smaller pitches. However, scanning type arrays are attractive due to their lower cost. In this thesis, design of a CMOS readout integrated circuit for an array of 288x4, n-on-p type HgCdTe long wave infrared detectors is presented. ROIC input preamplifier is current mirroring integration type due to low input impedance requirement. In order to increase SNR, time delay integration (TDI) on 4 detectors is applied with a super sampling rate of 3. ROIC has additional features of bidirectional TDI scanning, dead pixel deselection, automatic gain adjustment in response to pixel deselection, in addition to programmable four gain settings (up to 2.58pC storage), and programmable integration time. ROIC has four outputs with a dynamic range of 2.8V (from 1.7V to 4.5V) and input referred noise of 2989 electrons for an area of 13mm2. Two clocks: master clock and integration clock are required in order to operate the ROIC. Integration clock sets the integration time and adjust frame rate. Master clock maintains synchronization and can be adjusted up to 5MHz. ROIC can be programmed through both serial and parallel interface with full functionality but pixel deselection being allowed only in serial interface mode

Pulse frequency modulated DROICs with reduced quantization noise employing extended counting method

Reducing the system size and weight is a very competitive advantage in today’s IR market. A continuously growing effort has been shown to achieve digital output ROICs over the last decade with a primary concern to reduce the overall imaging system size and power by eliminating off chip ADCs and precise analog buffers as well as reducing the size of periphery boards. There is an unnamed industry standard of 20mK NETD for military IR imaging applications. A lower value is always desired to improve image quality or for track and search systems higher correct decision probabilities. Photon noise is the primary noise source and follow shot noise behavior and ideal SNR is limited with the square root of the stored charges. The limiting issue for higher SNR is due the limited charge handling capacity in a small pixel area. Recent works have shown DROICs with very high charge handling capacities on the order of giga electrons and SNR values as high as 90dB. The drawbacks of these works are the high quantization noise which makes their use limited to high flux scenes or low frame rate applications and high power dissipation which limits the use to small or moderate size array dimensions. In order to overcome these issues, this thesis has proposed circuit architectures with quantization noise levels lower than 200 electrons with 22 bit representation for a charge handling capacity of 2.34Ge-. The architecture relies on PFM pixel followed by a novel per pixel residue measurement method. A 32x32 prototype array has been fabricated and tested for verification of the proposed architecture. Design considerations have been followed for 256x256 array with a high frame rate of 400Hz and power dissipation of 22.21mW and a peak SNR of 71dB. Additionally low power operation of the proposed DROIC architecture with respect to ordinary PFM DROICs has been analyzed

Design of a ROIC for scanning type HgCdTe LWIR focal plane arrays

Design of a silicon readout integrated circuit (ROIC) for LWIR HgCdTe Focal Plane is presented. ROIC incorporates time delay integration (TDI) functionality over seven elements with a supersampling rate of three, increasing SNR and the spatial resolution. Novelty of this topology is inside TDI stage; integration of charges in TDI stage implemented in current domain by using switched current structures that reduces required area for chip and improves linearity performance. ROIC, in terms of functionality, is capable of bidirectional scan, programmable integration time and 5 gain settings at the input. Programming can be done parallel or serially with digital interface. ROIC can handle up to 3.5V dynamic range with the input stage to be direct injection (DI) type. With the load being 10pF capacitive in parallel with 1MΩ resistance, output settling time is less than 250nsec enabling the clock frequency up to 4MHz. The manufacturing technology is 0.35μm, double poly-Si, four-metal (3 metals and 1 top metal) 5V CMOS process

Realization of a ROIC for 72x4 PV-IR detectors

Silicon Readout Integrated Circuits (ROIC) for HgCdTe Focal Plane Arrays of 1x4 and 72x4 photovoltaic detectors are represented. The analog circuit blocks are completely identical for both, while the digital control circuit is modified to take into account the larger array size. The manufacturing technology is 0.35μm, double poly-Si, three-metal CMOS process. ROIC structure includes four elements TDI functioning with a super sampling rate of 3, bidirectional scanning, dead pixel de-selection, automatic gain adjustment in response to pixel deselection besides programmable four gain setting (up to 2.58pC storage), and programmable integration time. ROIC has four outputs with a dynamic range of 2.8V (from 1.2V to 4V) for an output load of 10pF capacitive in parallel with 1MΩ resistance, and operates at a clock frequency of 5 MHz. The input referred noise is less than 1037 μV with 460 fF integration capacitor, corresponding to 2978 electrons

4-bit SiGe phase shifter using distributed active switches and variable gain amplifier for x-band phased array applications

This paper presents a 4-bit digitally controlled phase shifter for X-band (8-12.5 GHz) phased-arrays, implemented in 0.25-mu m SiGe BiCMOS process. Distributed active switches are utilized in first three bits. On-chip inductances are used to provide 22.5 degrees phase shift steps. The placement and the geometry of these inductances are optimized for minimum phase error and insertion loss. In order to compensate the gain variations of this stage, a single stage variable gain amplifier is used. The fourth bit which provides 0/180 degrees phase shift is obtained in third amplification stage, with switching between common base - common emitter configuration. With utilization of this technique overall phase error is significantly decreased and overall gain is increased. The phase shifter achieves 7dB gain with 3 dB of gain error. 360 degrees phase shift is achieved in 4 bit resolution with a phase error of 0.5 degrees at center frequency of 10GHz, and maximum 22 degrees phase error in 4.5 GHz bandwidth. The chip size is 2150 mu m x 1040 mu m including the bondpads. These performance parameters are comparable with the state of the art using similar technology

Digital pixel readout integrated circuit architectures for LWIR

This paper presents and discusses digital pixel readout integrated circuit architectures for long wavelength infrared (LWIR) in CMOS technology. Presented architectures are designed for scanning and staring arrays type detectors respectively. For scanning arrays, digital time delay integration (TDI) is implemented on 8 pixels with sampling rate up to 3 using CMOS 180nm technology. Input referred noise of ROIC is below 750 rms electron meanwhile power dissipation is appreciably under 30mW. ROIC design is optimized to perform at room as well as cryogenic temperatures. For staring type arrays, a digital pixel architecture relying on coarse quantization with pulse frequency modulation (PFM) and novel approach of extended integration is presented.. It can achieve extreme charge handling capacity of 2.04Ge(-) with 20 bit output resolution and power dissipation below 350 nW in CMOS 90nm technology. Efficient mechanism of measuring the time to estimate the remaining charge on integration capacitor in order to achieve low SNR has employed

Low-power LVDS for digital readout circuits

This paper presents a mixed-signal LVDS driver in 90 nm CMOS technology. The designed LVDS core is to be used as a data link between Infrared Focal Plane Array (IRFPA) detector end and microprocessor input. Parallel data from 220 pixels of IRFPA is serialized by LVDS driver and read out to microprocessor. It also offers a reduced power consumption rate, high data transmission speed and utilizes dense placement of devices for area efficiency. The entire output driver circuit including input buffer draws 5mA while the output swing is 500mV at power supply of 1.2V for data rate of 6.4Gbps. Total LVDS chip area is 0.79 mm(2). Due to these features, the designed LVDS driver is suitable for purposes such as portable, high-speed imaging

Cryogenic measurements of a digital pixel readout integrated circuit for LWIR

This paper presents and discusses the cryogenic temperature (77K) measurement results of a digital readout integrated circuit (DROIC) for a 32x32 long wavelength infrared pixel sensor array designed in 90nm CMOS process. The chip achieves a signal-to-noise ratio (SNR) of 58dB with a charge handling capacity of 2.03Ge- at cryogenic temperature with 1.3mW of power dissipation. The performance of the readout is discussed in terms of power dissipation, charge handling capacity and SNR considering the fact that the process library models are not optimized for cryogenic temperature operation of the Metal-Oxide-Semiconductor (MOS) devices. These results provide an insight to foresee the design confrontations due to non-optimized device models for cryogenic temperatures particularly for short channel devices

An x-band 6-bit active phase shifter

This paper presents a 6-bit active phase shifter using a new vector-sum method for X-band (8-12 GHz) phased arrays in 0.13 mu m SiGe BiCMOS process. An RC filter is used to generate two orthogonal vectors which are then fed into four VGAs, two using the common-base and two using the common-emitter topology. This generates 4 vectors of 0 degrees, 90 degrees, 180 degrees and 270 degrees which are scaled and added by varying the gains of the VGAs to generate any phase between 0-360 degrees. The gains of the VGAs are adjusted with analog voltage control using the current-steering method. The outputs of the VGAs are connected together with a common load in order to add the vectors in current-domain. The phase shifter achieves < 5.6 degrees RMS phase error over 8-12 GHz and < 3.1 degrees RMS phase error over 9-11 GHz. The phase shifter has a power consumption of 16.6 mW from a 2V supply. The chip size is 850 mu m x 532 mu m including the probing pads. These performance parameters are comparable with the state of the art of the technology in literature

Treatment Framework : Traffic Steering via Source-Routing in SDN for Service Function Chaining

The middlebox architecture is long known for its inharmonious presence within the Internet architecture. Network functions realized in middleboxes are inclined to interpose end to end connections, modifying the datagram header or spawning new connections on behalf, which renders policy enforcement challenging. Moreover, their tight coupling with metadata makes its distributed persistence difficult, which hampers the flexible utilization and scalable provisioning of the middlebox infrastructure resources under varying loads. Existing attempts at mitigating these problems include middlebox placement, packet tagging and metadata migration; each solving only a part of the problem.Investing in the extensible nature of IPv6, the Treatment Framework (TRF) exploits source routing with the flavor of a discretionarily classifiable address space. Datagrams traverse the treatment domain with an extension header pushed and popped at the domain’s edges, for which forwarding takes place based on the information encoded within. The forwarding mechanics that leverage SDN consists of one match and three OpenFlow actions implementation, whereby TRF obviates the need for an underlying transport. Customizable address space allows providers to tailor routing aggregation to their middlebox farms topology, reducing the number of flow rules in the core to preinstallable sizes.Middleboxes in a treatment domain match traffic to the respective local policy based on the information encoded in the extension header. Extension headers are native to IPv6 and defined by standards, hence the middlebox modification problem is addressed without requiring alteration nor visibility into proprietary code. The framework resolves the policy enforcement problem altogether and allows asymmetric service chaining. While eliminating the flow setup time in the core, the framework’s footprint at ingress that push the extension header can get heavy with respect to flow churn rate.Det har länge varit känt att arkitektur baserad på mellanliggande utrustning, s.k.middlebox-arkitektur, inte alltid rimmar väl med Internet i övrigt. Nätverksfunktioner som implmenteras i middleboxar tenderar att leda till olika typer av förbindelser, modifierande av pakethuvuden eller nya uppkopplingar, vilket medför att det blir utmanande att verkställa olika typer av policy. Middlebox-lösningar är dessutom tätt kopplade till olika typer av metadata vilket innebär svårigheter för dess distribuerade fortlevnad och hindrar ett flexibelt utnyttjande och skalbar utbyggnad middleboxresurser under varierande trafiklast. Befintliga försök att mildra sådana problem inkluderar placering av mellanliggande utrustning, paketmärkning och migration av metadata; vart och ett av dessa löser endast delar av problemet.TRF (Treatment Framework) drar nytta av den utbyggbarhet som finns i IPv6 och använder vägval som styrs helt från avsändaren tillsammans med diskretionär adressrymd. IP-paketen traverserar en behandlings-domän och ett utökat pakethuvud används inom domänen. Det utökade pakethuvudet läggs till när paketet är på väg in i domänen och tas bort när paketet lämnar domänen. Inom domänen används information i det utökade pakethuvudet för att styra vidarebefordringen av paketet. Mekanismerna för vidarebefordring av paket använder sig av SDN och består av en match-operation och tre OpenFlow-åtgärder, varmed TRF kringgår behov av en underliggande transport. En anpass-ningsbart adressrymd gör det möjligt för leverantörer att skräddarsy vägvalsaggregering till sin middlebox-lösning, vilket gör att antalet trafikregler i kärnan av deras nät kan reduceras till förinställbara storlekar.En middlebox-lösning i en behandlings-domän matchar trafik mot respektive lokal policy baserad på information kodad i det utökade pakethuvudet. Tekniken med utökat pakethuvud är inbyggd i IPv6 och standardiserad vilket göra att paketmodifiering i en middlebox kan adresseras utan att kräva ändringar eller insyn i proprietär programvara. Ramverket löser problemet med verkställa olika typer av policy i sin helhet och medger skapandet av assymtriska kedjor av paketbehandlingstjänster. Tiden för att sätta upp paketflöden i kärnan av nätet kan elimineras, men det fotavtryck som ramverket ger i ingressdelen av domänen, där det utökade pakethuvudet skapas och läggs till inkommand paket, kan bli betydande med avseende på flödeshastigheten